1. Field of Invention
The present invention relates to voltage controlled oscillators (VCO) used in phase locked loop (PLL) circuits and, in particular, to methods and circuitry for reducing the required gain in the VCO to make the loop more stable and less susceptible to noise.
2. Discussion of the Related Art
PLL's have found many applications in the electronics industry. Among their uses are frequency modulated (FM) signal generation and decoding, clock recovery in digital communications, and clock multiplication in digital circuits. It is the latter of these three applications to which the present invention is directed.
FIG. 1 shows a block diagram of a typical PLL 100. The PLL is a feedback control system where the phase and frequency of an incoming signal (clk) is compared to a generated feedback signal (ffb). In the clock multiplication application, the phase comparator (PFD) 102 will generate pulses that tell the charge pump 104 whether the input signal (clk) is faster or slower than the feedback signal (ffb). If the input signal is faster, then the phase comparator 102 will generate an "UP" pulse that is proportional in width to the difference in phase between the signals. Likewise, if the input signal is slower, then the phase comparator 102 will generate a "DOWN" pulse that is proportional in width to the phase difference. These pulses are fed to the charge pump 104, which either charges or discharges the loop filter 106. The amount of charge or discharge is proportional to the phase difference since it is controlled by the pulse width of the UP or DOWN signal received by the charge pump 104. The voltage on the loop filter 106 controls the VCO 108. The VCO 108 produces a frequency that is proportional to the voltage at it's input. That frequency (fvco) is then fed back through a divider 110 to the phase comparator 102 as the generated feedback signal (ffb).
The purpose of the divider 110 in the feedback path is to multiply the clock up. This is by virtue of the fact that the phase comparator 102 will attempt to match the frequencies of the signals at it's inputs. For this to happen, the VCO 108 must be running N times faster than the incoming signal, since the VCO output gets divided by N before it gets compared to the incoming signal. The result is that the output of VCO 108 is equal to N times the input frequency and, hence, provides a clock multiplier.
A common problem in PLL's used for clock multiplication is that the gain in the VCO is extremely high. As stated earlier, the VCO is a circuit that will generate a frequency that is proportional to the voltage at it's input. The gain of the VCO is a measure of the change in the output frequency for a given change in the input voltage, and is given in Hz per Volt. It is desired to keep this gain term as low as possible to reduce the sensitivity of the VCO to noise on the tune node, and to keep the loop gain down. If there is too much gain in the loop, then it is difficult to attenuate the gain and achieve reasonable phase margin at the gain crossover point without using very large components in the filter. Three major sources of this high gain are lower power supplies, higher frequencies, and wide environmental variations.
A common goal in digital circuits is to reduce power consumption by lowering the supply voltage. By doing so, the gain goes up due to the reduced compliance range on the input of the VCO. As an example, assume a VCO must cover a 200 MHz range and the input to the VCO has a range from 0.5V above ground to 0.5V below the power supply. In a 5 volt system, the gain of the VCO would be 50 MHz/V (i.e. 200 MHz/(5-0.5)-(0+0.5)). However, if the power supply is lowered to 3.3 volts, the gain goes up to 87 MHz/V (i.e. 200 MHz/(3.3-0.5)-(0+0.5)). Higher frequencies also play a role in this. If a VCO must cover a 2.times. range of frequencies, the gain is doubled if that range is from 200 MHz to 400 MHz (i.e. 200 MHz range) rather than from 100 MHz to 200 MHz (i.e. 100 MHz range). Environmental variations are always present in integrated circuits and must be compensated for in the VCO. Even if the only frequency of interest is 100 MHz, the final VCO will likely need to cover a wide range of frequencies at typical conditions in order to cover variations in temperature, voltage and process. For instance, it may be that the VCO will need to cover a range of 50 MHz to 200 MHz at typical conditions so that, whether the circuit is running at hot or cold temperature, high or low voltage, or at the fast or slow process corner, the VCO will still have the 100 MHz desired frequency in it's operating range.
The problem with the implementation in FIG. 1 is that it makes no attempt to reduce the gain of the VCO 108. Although the loop will function (if designed correctly), it will be more susceptible to noise on the tune node, and will require larger components in the loop filter in order to attenuate the loop gain.